このタイミング図は Verilog ソース cpus-pdp11 に基づき、Unix V6 上の as(1) でアセンブルしたプログラムを実行して生成されます。
00 NOP
01 CLR R
02 COM R
03 INC R
04 DEC R
05 NEG R
06 ADC R
07 SBC R
08 TST R
09 SXT R
10 ROR R
11 ROL R
12 ASR R
13 ASL R
14 SWAB R
15 SXT R N0
16 MOV R R
17 CMP R R
18 BIT R R
19 BIC R R
20 BIS R R
21 ADD R R
22 SUB R R
23 MOV IMM R
24 ADD IMM R
25 CMP IMM R
26 BIS IMM R
27 MOV IND R
28 MOV R IND
29 MOV AUTOINC R
30 MOV AUTODEC R
31 MOV IDX R
32 MOVB IND R
33 BR TAKEN
34 BNE TAKEN
35 BNE NT
36 BEQ TAKEN
37 BGE TAKEN
38 BLT TAKEN
39 BCC TAKEN
40 BCS TAKEN
41 JSR R5
42 RTS R5
43 JMP IND
44 SOB TAKEN
45 SOB NT
46 MOVB R R
47 CLRB R
48 INCB R
49 CMPB R R
50 MODE0 REG
51 MODE1 IND
52 MODE2 AUTOINC
53 MODE4 AUTODEC
54 MODE6 IDX
55 MUL R R
56 DIV R R
57 ASH POS
58 ASH NEG
59 ASHC R
60 DIV OVF
61 RTI
62 RTT
00 NOP
01 CLR R
02 COM R
03 INC R
04 DEC R
05 NEG R
06 ADC R
07 SBC R
08 TST R
09 SXT R
10 ROR R
11 ROL R
12 ASR R
13 ASL R
14 SWAB R
15 SXT R N0
16 MOV R R
17 CMP R R
18 BIT R R
19 BIC R R
20 BIS R R
21 ADD R R
22 SUB R R
23 MOV IMM R
24 ADD IMM R
25 CMP IMM R
26 BIS IMM R
27 MOV IND R
28 MOV R IND
29 MOV AUTOINC R
30 MOV AUTODEC R
31 MOV IDX R
32 MOVB IND R
33 BR TAKEN
34 BNE TAKEN
35 BNE NT
36 BEQ TAKEN
37 BGE TAKEN
38 BLT TAKEN
39 BCC TAKEN
40 BCS TAKEN
41 JSR R5
42 RTS R5
43 JMP IND
44 SOB TAKEN
45 SOB NT
46 MOVB R R
47 CLRB R
48 INCB R
49 CMPB R R
50 MODE0 REG
51 MODE1 IND
52 MODE2 AUTOINC
53 MODE4 AUTODEC
54 MODE6 IDX
55 MUL R R
56 DIV R R
57 ASH POS
58 ASH NEG
59 ASHC R
60 DIV OVF