soft-FPGA
| 06 —
Intel 8080 / CP/M 2.2 RTL Simulator
Ver. 1.0.0 Ver.1.0.0 2026/06/13 14:42
vm80a
(decapped die RTL) →
Verilator
→
WASM
|
CP/M 2.2
+
custom BIOS
CP/M DOCS
02 CP/M Historical Value
03 Development Tools
12 CP/M Command Reference
14 cpm Command Reference
15 File Layout & Exchange
16 CP/M Software Sources
17 MBASIC Guide
18 BDS C Guide
19 Interactive Commands
20 Cycle Counter
22 Clock Measurement & Benchmark
23 WordMaster Guide
24 Turbo Pascal 3
25 Debug Panel & Logic Analyzer
30 Custom BIOS Implementation
52 Memory Map & I/O Ports
53 References
📷 Intel 8080 Timing Diagrams
Preset:
CP/M std
BDS C
Blank
Pause
Reset
Speed:
500 KHz (25%)
1.0 MHz (50%)
2.0 MHz (100%)
Max speed
Custom...
Theme:
Green
▼
Green
Amber
White
Light
Font:
6px
7px
8px
9px
10px
11px
12px
13px
14px
15px
16px
18px
20px
CPU
A:
--
|
F:
--------
|
BC:
----
DE:
----
HL:
----
|
SP:
----
|
PC:
----
FROZEN
KBD:
US
JIS
|
COPY
PASTE
^C
^D
^Z
ESC
TAB
WM ▼
│
▶ macro
■
Cursor:
^E ↑
^S ←
^X ↓
^D →
^A ←w
^F →w
|
Edit:
^G Del
^Y Del-L
^V Ins
^U Abrt
^J Help
|
File:
^KS Save
^KD Exit
^KQ Dsc
Logic Analyzer
LA ON
Fill
Hatch
❄ Freeze
▶ Next I/O
▶ Step
⚙ Trigger ▸
No Trigger
On I/O
On CALL
On RET
On Edge ↑
On Edge ↓
On Value
On Instruction
On Register
addr
dbus
port
io data
A
F
B
C
D
E
H
L
SP
PC
BC
DE
HL
IR
Set
Clear
⊙Trig
CL
«
‹
−
1/4x
1/2x
1x
2x
4x
8x
16x
32x
64x
+
›
»
📷 SS
Debug
Stack
I/O Log
Call Trace
WASM FS
Upload
Save
Drop / Upload → WASM FS | CP/M:
R filename
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