soft-FPGA

8-bit binary counter. Logic Analyzer with zoom, markers, freeze and edge/value triggers.

Traffic light finite state machine with state diagram view. The Logic Analyzer shows state, timer and lamps.

UART transmitter/receiver loopback. The Logic Analyzer decodes TX/RX frames into bytes.

MOS 6502 RTL simulator. Runs Woz Monitor and Integer BASIC. The Logic Analyzer disassembles each instruction.

Klaus Dormann's functional test suite running on the 6502 RTL core. Stop on any address or instruction with the Logic Analyzer trigger.

vm80a (decapped die RTL) running CP/M 2.2 with BDS C compiler. Includes I/O Bus Analyzer.

PDP-11/40 RTL running Unix V6. MMU PAR/PDR, bus waveforms, and R0–SP visible in real time.

Pong built from counters and comparators only — no CPU. 160×120 pixels, one pixel per clock. Move the paddle with W/S or the buttons; AUTO plays for you. The Logic Analyzer shows the ball, paddles, score and the scan counters.