Verilog RTL → Verilator → WebAssembly — retro CPU simulators running in your browser
| Example | Description | Tags |
|---|---|---|
|
01
Binary Counter
|
4-bit binary counter with ring-buffer waveform viewer.
|
counterrtlscope |
|
02
Traffic Light FSM
|
3-phase traffic light finite state machine with state diagram view.
|
FSMrtlscope |
|
03
UART (loopback)
|
UART transmitter/receiver loopback with logic analyzer view.
|
UARTrtlscope |
|
04
Apple-I / 6502
|
MOS 6502 RTL simulator. Runs Woz Monitor and Integer BASIC.
|
6502Apple-IBASIC |
|
05
6502 Dormann Test
|
Klaus Dormann's functional test suite running on the 6502 RTL core.
|
6502test |
|
06
Intel 8080 / CP/M 2.2
|
vm80a (decapped die RTL) running CP/M 2.2 with BDS C compiler. Includes I/O Bus Analyzer.
|
8080CP/MBDS C |